This is the first application filed for the present invention.
Not Applicable.
The present invention relates to synchronous data communication systems, and in particular to a method and apparatus for cross-connecting synchronous data communication streams with efficient memory utilization and transparent protocol conversion.
Modern synchronous data communications networks are typically designed to carry payload data using one of the Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) protocols. In each of these protocols, payload data is transported within frames in which data is conveniently organized into rows. Typically, each row is subdivided into a plurality of (e.g. ninety) data segments (columns), each of which may comprise one or more bytes of data. Normally, each row includes overhead (e.g. including transport overhead (TOH) and path overhead (POH)), payload data and fixed stuff. Under the SDH protocol, six data segments of overhead (three data segments each of TOH and POH) are grouped at the head of each row, followed by eighty-four data segments of payload data organized into twenty-one Tributary Units (TUs) of four data segments each. In contrast, a row of an SPE under the SONET protocol includes an overhead portion having three data segments of TOH and one data segment of POH. The payload data is organized into a set of twenty-eight Virtual Tributarys (VTs) of three data segments each, which are separated by one data segment of fixed stuff. Each of the TUs and VTs may be organized into a predetermined number of groups and/or channels.
In general, the TOH is arranged in a header portion of each row of a frame, while the POH, payload, and fixed stuff are arranged into an SPE, which may float within the envelope capacity of the frame. However, in the interests of simplifying the present description, the SPE is considered to be column-aligned to a fixed position within the frame, starting immediately after the TOH in the first row.
While each row of an SDH frame carries the same amount of payload and overhead (including fixed stuff) as a corresponding row of a SONET frame, the different row formats require that SDH and SONET traffic be transported over separate equipment. When it is necessary to cross-connect SDH and SONET traffic (for example, at a gateway connecting SDH and SONET networks) it is necessary to perform a SONET/SDH conversion as part of the cross-connection.
It is known to provide a cross-connection and protocol conversion function within an Application Specific Integrated Circuit (ASIC) in which a three port Random Access Memory (RAM) is used to provide a cross-connection between a plurality of input ports and a corresponding plurality of output ports. An associated core logic controls the writing of incoming data to the RAM and subsequent reading of outgoing data from the RAM to provide cross-connection, SONET/SDH frame format conversion and channel reordering functionality. Conventionally, the cross-connection function is performed on a row-by-row basis. Thus an entire incoming row of an incoming frame is written to a sector of the RAM. The data segments of the stored row are subsequently read from that sector of the RAM, perhaps with channel reordering and/or a frame format conversion to form at least part of one or more outgoing frame rows. In order to guarantee data integrity (i.e., temporal ordering of data segments), it is common to write the next incoming row to a second sector of the RAM during the read operation of the stored row. This eliminates a possibility that data of a stored row is overwritten before it is read out to an outgoing row.
The above described ASIC is capable of handling a large number of cross-connections, each involving high speed synchronous data streams. However, an important limitation on the capacity of the ASIC is the amount of RAM required to perform the cross-connection. In particular, cross-connection of an input data stream to its corresponding output data stream requires, for each row cross-connection, sufficient memory space to store two complete rows. Increasing the number of cross-connections which may be handled by the ASIC necessarily requires a corresponding increase in the amount of available RAM, and this in turn requires a larger and more complex core logic in order to provide addressing within the RAM.
Accordingly there remains a need for a method by which data streams can be cross-connected with an efficient utilization of RAM allocated to each cross-connection.
Accordingly, an object of the present invention is to provide a method and apparatus for cross-connecting synchronous data streams, in which the RAM allocated to each cross-connection is efficiently utilized.
Another object of the present invention is to provide a method and apparatus for cross-connecting synchronous data streams, in which the sequence in which incoming data is written into the RAM is independent of a format of the incoming data stream.
A further object of the present invention is to provide a method and apparatus for cross-connecting synchronous data streams, in which channel reordering and protocol conversions are implemented by controlling the sequence in which data is read from the RAM.
Accordingly, an aspect of the present invention provides a method of cross connecting an incoming data stream to one or more outgoing data streams. Each data stream comprises respective incoming and outgoing frames. Each frame includes one or more rows, each row comprising a respective plurality of data segments. The method comprises the steps of: providing a reserved memory space having a data storage capacity equal to an integer multiple of a data segment and less than one complete row; writing a data segment of an incoming row of an incoming frame to the reserved memory space; subsequently reading the data segment from the reserved memory space to an outgoing row of an outgoing frame; and timing the writing and reading steps such that the data segment is read from the reserved memory space before being over-written by another data segment.
A further aspect of the present invention provides a system for cross connecting an incoming data stream to one or more outgoing data streams, each of the incoming and outgoing data streams comprising respective incoming and outgoing frames, each frame including one or more rows, each row comprising a respective plurality of data segments, the system comprising: a reserved memory space having a data storage capacity equal to an integer multiple of a data segment and less than one complete row; means for writing a data segment of an incoming row of an incoming frame to the reserved memory space; means for reading the data segment of the incoming row to an outgoing row of an outgoing frame from the reserved memory space; and means for timing the writing and reading of the data segment such that the data segment is read from the reserved memory space before being over-written by another data segment
In a preferred embodiment of the present invention, each data segment comprises one or more bytes of data.
In a preferred embodiment of the present invention, the step of writing a data segment comprises a step of writing sequential data segments of the incoming frame to the reserved memory space in accordance with a predetermined first address sequence in which a start address for a given row commences immediately after a finish address of a previous row.
Preferably, the first address sequence is independent of a format of the incoming SPE.
Preferably, the first address sequence is different for each successive row of the incoming SPE and is repeated every three rows.
In a preferred embodiment of the present invention, the step of writing data segments of the incoming frame in accordance with the first address sequence comprises, for each row of the incoming frame, the steps of: writing sequential data segments of the incoming row to a sequential series of memory addresses between the base address and a predetermined threshold address; subsequently writing sequential data segments of the incoming row to a sequential series of memory addresses between a selected start address and the end address; and subsequently writing sequential data segments of the incoming row to a sequential series of memory addresses between the threshold address and a finish address.
Preferably, the predetermined threshold address is located at a fixed offset from the base address.
Preferably, the start address is selected on a basis of the finish address of an immediately preceding row. Still more preferably, the start address is selected to correspond to: the next available address after the threshold address if the finish address of the previous row corresponds to the end address; and otherwise the next available address after the finish address of the previous row.
In a preferred embodiment of the present invention, the step of reading the data segment comprises the step of reading data segments of each one of the one or more outgoing frames from the reserved memory space between the base address and the end address in accordance with a predetermined second address sequence. Preferably the step of reading data segments in accordance with the second address sequence comprises, in respect of each incoming row, the steps of: successively accessing each one of a plurality of blocks of memory addresses, each block of memory addresses being smaller than the reserved memory address space and comprising a respective predetermined number of data segments; and reading one or more data segments of an outgoing frame from an accessed block of memory addresses.
In a preferred embodiment of the present invention, the step of successively accessing each one of a plurality of blocks of memory address comprises: accessing one or more header blocks corresponding to an overhead portion of the incoming row; and accessing a plurality of payload memory blocks, each payload memory block corresponding to a respective payload portion of the incoming row.
In embodiments of the invention, each one of the one or more header blocks are preferably accessed in succession, and then each one of the plurality of payload blocks are successively accessed. Each payload memory block preferably comprises a predetermined number of contiguous data segments. In some embodiments of the invention, each payload memory block comprises 21 contiguous data segments. In this case, four payload memory blocks are accessed to read data segments of an entire row.
In embodiments of the invention, a payload portion of the incoming row includes at least one data segment of embedded fixed stuff, and in such cases the payload memory blocks are preferably arranged to exclude the embedded fixed stuff data segments. At least one fixed stuff data segment can be accessed prior to accessing each payload memory block.
In embodiments of the present invention, each payload memory block comprises one or more respective sub-blocks, which may be accessed simultaneously. Preferably, each payload memory block encompasses a predetermined number of data segments, the predetermined number being defined by a sum of a number of data segments comprising each respective sub-block. Still more preferably, the predetermined number of data segments encompassed by each payload memory block is the same for every block. In one embodiment of the invention, the predetermined number of data segments within each block is 28.
The step of reading one or more data segments of an outgoing row from an accessed block of memory addresses comprises reading each data segment within the accessed block sequentially, or in accordance with provisioned channel reordering.